3.17.33 Nios II Options

These are the options defined for the Altera Nios II processor.

-G num

Put global and static objects less than or equal to num bytes into the small data or BSS sections instead of the normal data or BSS sections. The default value of num is 8.

-mgpopt

-mno-gpopt

Generate (do not generate) GP-relative accesses for objects in the small data or BSS sections. The default is -mgpopt except when -fpic or -fPIC is specified to generate position-independent code. Note that the Nios II ABI does not permit GP-relative accesses from shared libraries.

You may need to specify -mno-gpopt explicitly when building programs that include large amounts of small data, including large GOT data sections. In this case, the 16-bit offset for GP-relative addressing may not be large enough to allow access to the entire small data section.

-mel

-meb

Generate little-endian (default) or big-endian (experimental) code, respectively.

-mbypass-cache

-mno-bypass-cache

Force all load and store instructions to always bypass cache by using I/O variants of the instructions. The default is not to bypass the cache.

-mno-cache-volatile

-mcache-volatile

Volatile memory access bypass the cache using the I/O variants of the load and store instructions. The default is not to bypass the cache.

-mno-fast-sw-div

-mfast-sw-div

Do not use table-based fast divide for small numbers. The default is to use the fast divide at -O3 and above.

-mno-hw-mul

-mhw-mul

-mno-hw-mulx

-mhw-mulx

-mno-hw-div

-mhw-div

Enable or disable emitting mul, mulx and div family of instructions by the compiler. The default is to emit mul and not emit div and mulx.

-mcustom-insn=N

-mno-custom-insn

Each -mcustom-insn=N option enables use of a custom instruction with encoding N when generating code that uses insn. For example, -mcustom-fadds=253 generates custom instruction 253 for single-precision floating-point add operations instead of the default behavior of using a library call.

The following values of insn are supported. Except as otherwise noted, floating-point operations are expected to be implemented with normal IEEE 754 semantics and correspond directly to the C operators or the equivalent GCC built-in functions (see Other Builtins).

Single-precision floating point:

‘fadds’, ‘fsubs’, ‘fdivs’, ‘fmuls’

Binary arithmetic operations.

‘fnegs’

Unary negation.

‘fabss’

Unary absolute value.

‘fcmpeqs’, ‘fcmpges’, ‘fcmpgts’, ‘fcmples’, ‘fcmplts’, ‘fcmpnes’

Comparison operations.

‘fmins’, ‘fmaxs’

Floating-point minimum and maximum. These instructions are only generated if -ffinite-math-only is specified.

‘fsqrts’

Unary square root operation.

‘fcoss’, ‘fsins’, ‘ftans’, ‘fatans’, ‘fexps’, ‘flogs’

Floating-point trigonometric and exponential functions. These instructions are only generated if -funsafe-math-optimizations is also specified.

Double-precision floating point:

‘faddd’, ‘fsubd’, ‘fdivd’, ‘fmuld’

Binary arithmetic operations.

‘fnegd’

Unary negation.

‘fabsd’

Unary absolute value.

‘fcmpeqd’, ‘fcmpged’, ‘fcmpgtd’, ‘fcmpled’, ‘fcmpltd’, ‘fcmpned’

Comparison operations.

‘fmind’, ‘fmaxd’

Double-precision minimum and maximum. These instructions are only generated if -ffinite-math-only is specified.

‘fsqrtd’

Unary square root operation.

‘fcosd’, ‘fsind’, ‘ftand’, ‘fatand’, ‘fexpd’, ‘flogd’

Double-precision trigonometric and exponential functions. These instructions are only generated if -funsafe-math-optimizations is also specified.

Conversions:

‘fextsd’

Conversion from single precision to double precision.

‘ftruncds’

Conversion from double precision to single precision.

‘fixsi’, ‘fixsu’, ‘fixdi’, ‘fixdu’

Conversion from floating point to signed or unsigned integer types, with truncation towards zero.

‘floatis’, ‘floatus’, ‘floatid’, ‘floatud’

Conversion from signed or unsigned integer types to floating-point types.

In addition, all of the following transfer instructions for internal registers X and Y must be provided to use any of the double-precision floating-point instructions. Custom instructions taking two double-precision source operands expect the first operand in the 64-bit register X. The other operand (or only operand of a unary operation) is given to the custom arithmetic instruction with the least significant half in source register src1 and the most significant half in src2. A custom instruction that returns a double-precision result returns the most significant 32 bits in the destination register and the other half in 32-bit register Y. GCC automatically generates the necessary code sequences to write register X and/or read register Y when double-precision floating-point instructions are used.

‘fwrx’

Write src1 into the least significant half of X and src2 into the most significant half of X.

‘fwry’

Write src1 into Y.

‘frdxhi’, ‘frdxlo’

Read the most or least (respectively) significant half of X and store it in dest.

‘frdy’

Read the value of Y and store it into dest.

Note that you can gain more local control over generation of Nios II custom instructions by using the target("custom-insn=N") and target("no-custom-insn") function attributes (see Function Attributes) or pragmas (see Function Specific Option Pragmas).

-mcustom-fpu-cfg=name

This option enables a predefined, named set of custom instruction encodings (see -mcustom-insn above). Currently, the following sets are defined:

-mcustom-fpu-cfg=60-1 is equivalent to:

-mcustom-fmuls=252 
-mcustom-fadds=253 
-mcustom-fsubs=254 
-fsingle-precision-constant

-mcustom-fpu-cfg=60-2 is equivalent to:

-mcustom-fmuls=252 
-mcustom-fadds=253 
-mcustom-fsubs=254 
-mcustom-fdivs=255 
-fsingle-precision-constant

-mcustom-fpu-cfg=72-3 is equivalent to:

-mcustom-floatus=243 
-mcustom-fixsi=244 
-mcustom-floatis=245 
-mcustom-fcmpgts=246 
-mcustom-fcmples=249 
-mcustom-fcmpeqs=250 
-mcustom-fcmpnes=251 
-mcustom-fmuls=252 
-mcustom-fadds=253 
-mcustom-fsubs=254 
-mcustom-fdivs=255 
-fsingle-precision-constant

Custom instruction assignments given by individual -mcustom-insn= options override those given by -mcustom-fpu-cfg=, regardless of the order of the options on the command line.

Note that you can gain more local control over selection of a FPU configuration by using the target("custom-fpu-cfg=name") function attribute (see Function Attributes) or pragma (see Function Specific Option Pragmas).

These additional ‘-m’ options are available for the Altera Nios II ELF (bare-metal) target:

-mhal

Link with HAL BSP. This suppresses linking with the GCC-provided C runtime startup and termination code, and is typically used in conjunction with -msys-crt0= to specify the location of the alternate startup code provided by the HAL BSP.

-msmallc

Link with a limited version of the C library, -lsmallc, rather than Newlib.

-msys-crt0=startfile

startfile is the file name of the startfile (crt0) to use when linking. This option is only useful in conjunction with -mhal.

-msys-lib=systemlib

systemlib is the library name of the library that provides low-level system calls required by the C library, e.g. read and write. This option is typically used to link with a library provided by a HAL BSP.