These ‘-m
’ options are defined for the ARM port:
-mabi=
name
apcs-gnu
’, ‘atpcs
’, ‘aapcs
’, ‘aapcs-linux
’ and ‘iwmmxt
’. -mapcs-frame
-fomit-frame-pointer
with this option causes the stack frames not to be generated for leaf functions. The default is -mno-apcs-frame
. This option is deprecated. -mapcs
-mapcs-frame
and is deprecated. -mthumb-interwork
-mno-thumb-interwork
, since slightly larger code is generated when -mthumb-interwork
is specified. In AAPCS configurations this option is meaningless. -mno-sched-prolog
-msched-prolog
. -mfloat-abi=
name
soft
’, ‘softfp
’ and ‘hard
’. Specifying ‘soft
’ causes GCC to generate output containing library calls for floating-point operations. ‘softfp
’ allows the generation of code using hardware floating-point instructions, but still uses the soft-float calling conventions. ‘hard
’ allows generation of floating-point instructions and uses FPU-specific calling conventions.
The default depends on the specific target configuration. Note that the hard-float and soft-float ABIs are not link-compatible; you must compile your entire program with the same ABI, and link with a compatible set of libraries.
-mlittle-endian
-mbig-endian
-march=
name
-mcpu=
option. Permissible names are: ‘armv2
’, ‘armv2a
’, ‘armv3
’, ‘armv3m
’, ‘armv4
’, ‘armv4t
’, ‘armv5
’, ‘armv5t
’, ‘armv5e
’, ‘armv5te
’, ‘armv6
’, ‘armv6j
’, ‘armv6t2
’, ‘armv6z
’, ‘armv6kz
’, ‘armv6-m
’, ‘armv7
’, ‘armv7-a
’, ‘armv7-r
’, ‘armv7-m
’, ‘armv7e-m
’, ‘armv7ve
’, ‘armv8-a
’, ‘armv8-a+crc
’, ‘armv8.1-a
’, ‘armv8.1-a+crc
’, ‘iwmmxt
’, ‘iwmmxt2
’, ‘ep9312
’. Architecture revisions older than armv4t
are deprecated.
-march=armv7ve
is the armv7-a architecture with virtualization extensions.
-march=armv8-a+crc
enables code generation for the ARMv8-A architecture together with the optional CRC32 extensions.
-march=native
causes the compiler to auto-detect the architecture of the build computer. At present, this feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect.
-mtune=
name
arm2
’, ‘arm250
’, ‘arm3
’, ‘arm6
’, ‘arm60
’, ‘arm600
’, ‘arm610
’, ‘arm620
’, ‘arm7
’, ‘arm7m
’, ‘arm7d
’, ‘arm7dm
’, ‘arm7di
’, ‘arm7dmi
’, ‘arm70
’, ‘arm700
’, ‘arm700i
’, ‘arm710
’, ‘arm710c
’, ‘arm7100
’, ‘arm720
’, ‘arm7500
’, ‘arm7500fe
’, ‘arm7tdmi
’, ‘arm7tdmi-s
’, ‘arm710t
’, ‘arm720t
’, ‘arm740t
’, ‘strongarm
’, ‘strongarm110
’, ‘strongarm1100
’, ‘strongarm1110
’, ‘arm8
’, ‘arm810
’, ‘arm9
’, ‘arm9e
’, ‘arm920
’, ‘arm920t
’, ‘arm922t
’, ‘arm946e-s
’, ‘arm966e-s
’, ‘arm968e-s
’, ‘arm926ej-s
’, ‘arm940t
’, ‘arm9tdmi
’, ‘arm10tdmi
’, ‘arm1020t
’, ‘arm1026ej-s
’, ‘arm10e
’, ‘arm1020e
’, ‘arm1022e
’, ‘arm1136j-s
’, ‘arm1136jf-s
’, ‘mpcore
’, ‘mpcorenovfp
’, ‘arm1156t2-s
’, ‘arm1156t2f-s
’, ‘arm1176jz-s
’, ‘arm1176jzf-s
’, ‘generic-armv7-a
’, ‘cortex-a5
’, ‘cortex-a7
’, ‘cortex-a8
’, ‘cortex-a9
’, ‘cortex-a12
’, ‘cortex-a15
’, ‘cortex-a17
’, ‘cortex-a32
’, ‘cortex-a35
’, ‘cortex-a53
’, ‘cortex-a57
’, ‘cortex-a72
’, ‘cortex-r4
’, ‘cortex-r4f
’, ‘cortex-r5
’, ‘cortex-r7
’, ‘cortex-r8
’, ‘cortex-m7
’, ‘cortex-m4
’, ‘cortex-m3
’, ‘cortex-m1
’, ‘cortex-m0
’, ‘cortex-m0plus
’, ‘cortex-m1.small-multiply
’, ‘cortex-m0.small-multiply
’, ‘cortex-m0plus.small-multiply
’, ‘exynos-m1
’, ‘qdf24xx
’, ‘marvell-pj4
’, ‘xscale
’, ‘iwmmxt
’, ‘iwmmxt2
’, ‘ep9312
’, ‘fa526
’, ‘fa626
’, ‘fa606te
’, ‘fa626te
’, ‘fmp626
’, ‘fa726te
’, ‘xgene1
’. Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system. Permissible names are: ‘cortex-a15.cortex-a7
’, ‘cortex-a17.cortex-a7
’, ‘cortex-a57.cortex-a53
’, ‘cortex-a72.cortex-a53
’.
-mtune=generic-arch specifies that GCC should tune the performance for a blend of processors within architecture arch. The aim is to generate code that run well on the current most popular processors, balancing between optimizations that benefit some CPUs in the range, and avoiding performance pitfalls of other CPUs. The effects of this option may change in future GCC versions as CPU models come and go.
-mtune=native
causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect.
-mcpu=
name
-march
) and the ARM processor type for which to tune for performance (as if specified by -mtune
). Where this option is used in conjunction with -march
or -mtune
, those options take precedence over the appropriate part of this option. Permissible names for this option are the same as those for -mtune
.
-mcpu=generic-arch is also permissible, and is equivalent to -march=arch -mtune=generic-arch. See -mtune
for more information.
-mcpu=native
causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect.
-mfpu=
name
vfp
’, ‘vfpv3
’, ‘vfpv3-fp16
’, ‘vfpv3-d16
’, ‘vfpv3-d16-fp16
’, ‘vfpv3xd
’, ‘vfpv3xd-fp16
’, ‘neon
’, ‘neon-fp16
’, ‘vfpv4
’, ‘vfpv4-d16
’, ‘fpv4-sp-d16
’, ‘neon-vfpv4
’, ‘fpv5-d16
’, ‘fpv5-sp-d16
’, ‘fp-armv8
’, ‘neon-fp-armv8
’ and ‘crypto-neon-fp-armv8
’. If -msoft-float
is specified this specifies the format of floating-point values.
If the selected floating-point hardware includes the NEON extension (e.g. -mfpu
=‘neon
’), note that floating-point operations are not generated by GCC's auto-vectorization pass unless -funsafe-math-optimizations
is also specified. This is because NEON hardware does not fully implement the IEEE 754 standard for floating-point arithmetic (in particular denormal values are treated as zero), so the use of NEON instructions may lead to a loss of precision.
You can also set the fpu name at function level by using the target("fpu=")
function attributes (see ARM Function Attributes) or pragmas (see Function Specific Option Pragmas).
-mfp16-format=
name
__fp16
half-precision floating-point type. Permissible names are ‘none
’, ‘ieee
’, and ‘alternative
’; the default is ‘none
’, in which case the __fp16
type is not defined. See Half-Precision, for more information. -mstructure-size-boundary=
n
Specifying a larger number can produce faster, more efficient code, but can also increase the size of the program. Different values are potentially incompatible. Code compiled with one value cannot necessarily expect to work with code or libraries compiled with another value, if they exchange information using structures or unions.
-mabort-on-noreturn
abort
at the end of a noreturn
function. It is executed if the function tries to return. -mlong-calls
-mno-long-calls
Even if this switch is enabled, not all function calls are turned into long calls. The heuristic is that static functions, functions that have the short_call
attribute, functions that are inside the scope of a #pragma no_long_calls
directive, and functions whose definitions have already been compiled within the current compilation unit are not turned into long calls. The exceptions to this rule are that weak function definitions, functions with the long_call
attribute or the section
attribute, and functions that are within the scope of a #pragma long_calls
directive are always turned into long calls.
This feature is not enabled by default. Specifying -mno-long-calls
restores the default behavior, as does placing the function calls within the scope of a #pragma
long_calls_off
directive. Note these switches have no effect on how the compiler generates code to handle function calls via function pointers.
-msingle-pic-base
-mpic-register=
reg
R9
’ if target is EABI based or stack-checking is enabled, otherwise the default is ‘R10
’. -mpic-data-is-text-relative
-mpoke-function-name
t0 .ascii "arm_poke_function_name", 0 .align t1 .word 0xff000000 + (t1 - t0) arm_poke_function_name mov ip, sp stmfd sp!, {fp, ip, lr, pc} sub fp, ip, #4
When performing a stack backtrace, code can inspect the value of pc
stored at fp + 0
. If the trace function then looks at location pc - 12
and the top 8 bits are set, then we know that there is a function name embedded immediately preceding this location and has length ((pc[-3]) & 0xff000000)
.
-mthumb
-marm
--with-mode=
state configure option. You can also override the ARM and Thumb mode for each function by using the target("thumb")
and target("arm")
function attributes (see ARM Function Attributes) or pragmas (see Function Specific Option Pragmas).
-mtpcs-frame
-mno-tpcs-frame
. -mtpcs-leaf-frame
-mno-apcs-leaf-frame
. -mcallee-super-interworking
-mcaller-super-interworking
-mtp=
name
soft
’, which generates calls to __aeabi_read_tp
, ‘cp15
’, which fetches the thread pointer from cp15
directly (supported in the arm6k architecture), and ‘auto
’, which uses the best available method for the selected processor. The default setting is ‘auto
’. -mtls-dialect=
dialect
gnu
’ and ‘gnu2
’. The ‘gnu
’ dialect selects the original GNU scheme for supporting local and global dynamic TLS models. The ‘gnu2
’ dialect selects the GNU descriptor scheme, which provides better performance for shared libraries. The GNU descriptor scheme is compatible with the original scheme, but does require new assembler, linker and library support. Initial and local exec TLS models are unaffected by this option and always use the original scheme. -mword-relocations
-fpic
or -fPIC
is specified. -mfix-cortex-m3-ldrd
ldrd
instructions with overlapping destination and base registers are used. This option avoids generating these instructions. This option is enabled by default when -mcpu=cortex-m3
is specified. -munaligned-access
-mno-unaligned-access
The ARM attribute Tag_CPU_unaligned_access
is set in the generated object file to either true or false, depending upon the setting of this option. If unaligned access is enabled then the preprocessor symbol __ARM_FEATURE_UNALIGNED
is also defined.
-mneon-for-64bits
-mslow-flash-data
-masm-syntax-unified
-mrestrict-it
-mprint-tune-info
© Free Software Foundation
Licensed under the GNU Free Documentation License, Version 1.3.
https://gcc.gnu.org/onlinedocs/gcc-6.3.0/gcc/ARM-Options.html