These ‘-m’ options are defined for the IBM RS/6000 and PowerPC:
-mpowerpc-gpopt-mno-powerpc-gpopt-mpowerpc-gfxopt-mno-powerpc-gfxopt-mpowerpc64-mno-powerpc64-mmfcrf-mno-mfcrf-mpopcntb-mno-popcntb-mpopcntd-mno-popcntd-mfprnd-mno-fprnd-mcmpb-mno-cmpb-mmfpgpr-mno-mfpgpr-mhard-dfp-mno-hard-dfpSpecifying -mpowerpc-gpopt allows GCC to use the optional PowerPC architecture instructions in the General Purpose group, including floating-point square root. Specifying -mpowerpc-gfxopt allows GCC to use the optional PowerPC architecture instructions in the Graphics group, including floating-point select.
The -mmfcrf option allows GCC to generate the move from condition register field instruction implemented on the POWER4 processor and other processors that support the PowerPC V2.01 architecture. The -mpopcntb option allows GCC to generate the popcount and double-precision FP reciprocal estimate instruction implemented on the POWER5 processor and other processors that support the PowerPC V2.02 architecture. The -mpopcntd option allows GCC to generate the popcount instruction implemented on the POWER7 processor and other processors that support the PowerPC V2.06 architecture. The -mfprnd option allows GCC to generate the FP round to integer instructions implemented on the POWER5+ processor and other processors that support the PowerPC V2.03 architecture. The -mcmpb option allows GCC to generate the compare bytes instruction implemented on the POWER6 processor and other processors that support the PowerPC V2.05 architecture. The -mmfpgpr option allows GCC to generate the FP move to/from general-purpose register instructions implemented on the POWER6X processor and other processors that support the extended PowerPC V2.05 architecture. The -mhard-dfp option allows GCC to generate the decimal floating-point instructions implemented on some POWER processors.
The -mpowerpc64 option allows GCC to generate the additional 64-bit instructions that are found in the full PowerPC64 architecture and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to -mno-powerpc64.
-mcpu=cpu_type
401’, ‘403’, ‘405’, ‘405fp’, ‘440’, ‘440fp’, ‘464’, ‘464fp’, ‘476’, ‘476fp’, ‘505’, ‘601’, ‘602’, ‘603’, ‘603e’, ‘604’, ‘604e’, ‘620’, ‘630’, ‘740’, ‘7400’, ‘7450’, ‘750’, ‘801’, ‘821’, ‘823’, ‘860’, ‘970’, ‘8540’, ‘a2’, ‘e300c2’, ‘e300c3’, ‘e500mc’, ‘e500mc64’, ‘e5500’, ‘e6500’, ‘ec603e’, ‘G3’, ‘G4’, ‘G5’, ‘titan’, ‘power3’, ‘power4’, ‘power5’, ‘power5+’, ‘power6’, ‘power6x’, ‘power7’, ‘power8’, ‘powerpc’, ‘powerpc64’, ‘powerpc64le’, and ‘rs64’. -mcpu=powerpc, -mcpu=powerpc64, and -mcpu=powerpc64le specify pure 32-bit PowerPC (either endian), 64-bit big endian PowerPC and 64-bit little endian PowerPC architecture machine types, with an appropriate, generic processor model assumed for scheduling purposes.
The other options specify a specific processor. Code generated under those options runs best on that processor, and may not run at all on others.
The -mcpu options automatically enable or disable the following options:
-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple -mpopcntb -mpopcntd -mpowerpc64 -mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float -msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx -mcrypto -mdirect-move -mpower8-fusion -mpower8-vector -mquad-memory -mquad-memory-atomic
The particular options set for any particular CPU varies between compiler versions, depending on what setting seems to produce optimal code for that CPU; it doesn't necessarily reflect the actual hardware's capabilities. If you wish to set an individual option to a particular value, you may specify it after the -mcpu option, like -mcpu=970 -mno-altivec.
On AIX, the -maltivec and -mpowerpc64 options are not enabled or disabled by the -mcpu option at present because AIX does not have full support for these options. You may still enable or disable them individually if you're sure it'll work in your environment.
-mtune=cpu_type
-mtune as for -mcpu. If both are specified, the code generated uses the architecture and registers set by -mcpu, but the scheduling parameters set by -mtune. -mcmodel=small-mcmodel=medium-mcmodel=large-maltivec-mno-altivec-mabi=altivec to adjust the current ABI with AltiVec ABI enhancements. When -maltivec is used, rather than -maltivec=le or -maltivec=be, the element order for Altivec intrinsics such as vec_splat, vec_extract, and vec_insert match array element order corresponding to the endianness of the target. That is, element zero identifies the leftmost element in a vector register when targeting a big-endian platform, and identifies the rightmost element in a vector register when targeting a little-endian platform.
-maltivec=beThe element order is used to interpret element numbers in Altivec intrinsics such as vec_splat, vec_extract, and vec_insert. By default, these match array element order corresponding to the endianness for the target.
-maltivec=leThe element order is used to interpret element numbers in Altivec intrinsics such as vec_splat, vec_extract, and vec_insert. By default, these match array element order corresponding to the endianness for the target.
-mvrsave-mno-vrsave-mgen-cell-microcode-mwarn-cell-microcode-msecure-pltld and ld.so to build executables and shared libraries with non-executable .plt and .got sections. This is a PowerPC 32-bit SYSV ABI option. -mbss-plt.plt section that ld.so fills in, and requires .plt and .got sections that are both writable and executable. This is a PowerPC 32-bit SYSV ABI option. -misel-mno-isel-misel=yes/no
-misel and -mno-isel instead. -mspe-mno-spe-mpaired-mno-paired-mspe=yes/no
-mspe and -mno-spe instead. -mvsx-mno-vsx-mcrypto-mno-crypto-mdirect-move-mno-direct-move-mpower8-fusion-mno-power8-fusion-mpower8-vector-mno-power8-vector-mquad-memory-mno-quad-memory-mquad-memory option requires use of 64-bit mode. -mquad-memory-atomic-mno-quad-memory-atomic-mquad-memory-atomic option requires use of 64-bit mode. -mupper-regs-df-mno-upper-regs-df-mupper-regs-df is turned on by default if you use any of the -mcpu=power7, -mcpu=power8, or -mvsx options. -mupper-regs-sf-mno-upper-regs-sf-mupper-regs-sf is turned on by default if you use either of the -mcpu=power8 or -mpower8-vector options. -mupper-regs-mno-upper-regsIf the -mno-upper-regs option is used, it turns off both -mupper-regs-sf and -mupper-regs-df options.
-mfloat-gprs=yes/single/double/no-mfloat-gprsThe argument ‘yes’ or ‘single’ enables the use of single-precision floating-point operations.
The argument ‘double’ enables the use of single and double-precision floating-point operations.
The argument ‘no’ disables floating-point operations on the general-purpose registers.
This option is currently only available on the MPC854x.
-m32-m64-mpowerpc64. -mfull-toc-mno-fp-in-toc-mno-sum-in-toc-mminimal-toc-mfull-toc option is selected by default. In that case, GCC allocates at least one TOC entry for each unique non-automatic variable reference in your program. GCC also places floating-point constants in the TOC. However, only 16,384 entries are available in the TOC. If you receive a linker error message that saying you have overflowed the available TOC space, you can reduce the amount of TOC space used with the -mno-fp-in-toc and -mno-sum-in-toc options. -mno-fp-in-toc prevents GCC from putting floating-point constants in the TOC and -mno-sum-in-toc forces GCC to generate code to calculate the sum of an address and a constant at run time instead of putting that sum into the TOC. You may specify one or both of these options. Each causes GCC to produce very slightly slower and larger code at the expense of conserving TOC space.
If you still run out of space in the TOC even when you specify both of these options, specify -mminimal-toc instead. This option causes GCC to make only one TOC entry for every file. When you specify this option, GCC produces code that is slower and larger but which uses extremely little TOC space. You may wish to use this option only on files that contain less frequently-executed code.
-maix64-maix32long type, and the infrastructure needed to support them. Specifying -maix64 implies -mpowerpc64, while -maix32 disables the 64-bit ABI and implies -mno-powerpc64. GCC defaults to -maix32. -mxl-compat-mno-xl-compatThe AIX calling convention was extended but not initially documented to handle an obscure K&R C case of calling a function that takes the address of its arguments with fewer arguments than declared. IBM XL compilers access floating-point arguments that do not fit in the RSA from the stack when a subroutine is compiled without optimization. Because always storing floating-point arguments on the stack is inefficient and rarely needed, this option is not enabled by default and only is necessary when calling subroutines compiled by IBM XL compilers without optimization.
-mpe/usr/lpp/ppe.poe/), or the specs file must be overridden with the -specs= option to specify the appropriate directory location. The Parallel Environment does not support threads, so the -mpe option and the -pthread option are incompatible. -malign-natural-malign-power-malign-natural overrides the ABI-defined alignment of larger types, such as floating-point doubles, on their natural size-based boundary. The option -malign-power instructs GCC to follow the ABI-specified alignment rules. GCC defaults to the standard alignment defined in the ABI. On 64-bit Darwin, natural alignment is the default, and -malign-power is not supported.
-msoft-float-mhard-float-msoft-float option, and pass the option to GCC when linking. -msingle-float-mdouble-float-mdouble-float implies -msingle-float. -msimple-fpusqrt and div instructions for hardware floating-point unit. -mfpu=name
sp_lite’ (equivalent to -msingle-float -msimple-fpu), ‘dp_lite’ (equivalent to -mdouble-float -msimple-fpu), ‘sp_full’ (equivalent to -msingle-float), and ‘dp_full’ (equivalent to -mdouble-float). -mxilinx-fpu-mmultiple-mno-multiple-mmultiple on little-endian PowerPC systems, since those instructions do not work when the processor is in little-endian mode. The exceptions are PPC740 and PPC750 which permit these instructions in little-endian mode. -mstring-mno-string-mstring on little-endian PowerPC systems, since those instructions do not work when the processor is in little-endian mode. The exceptions are PPC740 and PPC750 which permit these instructions in little-endian mode. -mupdate-mno-update-mno-update, there is a small window between the time that the stack pointer is updated and the address of the previous frame is stored, which means code that walks the stack frame across interrupts or signals may get corrupted data. -mavoid-indexed-addresses-mno-avoid-indexed-addresses-mfused-madd-mno-fused-madd-mfused-madd option is now mapped to the machine-independent -ffp-contract=fast option, and -mno-fused-madd is mapped to -ffp-contract=off. -mmulhw-mno-mulhw-mdlmzb-mno-dlmzbdlmzb’ instruction on the IBM 405, 440, 464 and 476 processors. This instruction is generated by default when targeting those processors. -mno-bit-align-mbit-alignFor example, by default a structure containing nothing but 8 unsigned bit-fields of length 1 is aligned to a 4-byte boundary and has a size of 4 bytes. By using -mno-bit-align, the structure is aligned to a 1-byte boundary and is 1 byte in size.
-mno-strict-align-mstrict-align-mrelocatable-mno-relocatable.got2 and 4-byte locations listed in the .fixup section, a table of 32-bit addresses generated by this option. For this to work, all objects linked together must be compiled with -mrelocatable or -mrelocatable-lib. -mrelocatable code aligns the stack to an 8-byte boundary. -mrelocatable-lib-mno-relocatable-lib-mrelocatable, -mrelocatable-lib generates a .fixup section to allow static executables to be relocated at run time, but -mrelocatable-lib does not use the smaller stack alignment of -mrelocatable. Objects compiled with -mrelocatable-lib may be linked with objects compiled with any combination of the -mrelocatable options. -mno-toc-mtoc-mlittle-mlittle-endian-mlittle-endian option is the same as -mlittle. -mbig-mbig-endian-mbig-endian option is the same as -mbig. -mdynamic-no-pic-msingle-pic-base-mprioritize-restricted-insns=priority
0’, ‘1’, or ‘2’ to assign no, highest, or second-highest (respectively) priority to dispatch-slot restricted instructions. -msched-costly-dep=dependence_type
no’all’true_store_to_load’store_to_load’-minsert-sched-nops=scheme
no’pad’regroup_exact’-mcall-sysvpowerpc-*-eabiaix’. -mcall-sysv-eabi-mcall-eabi-mcall-sysv and -meabi options. -mcall-sysv-noeabi-mcall-sysv and -mno-eabi options. -mcall-aixdesc-mcall-linux-mcall-freebsd-mcall-netbsd-mcall-openbsd-maix-struct-return-msvr4-struct-return-mabi=abi-type
altivec’, ‘no-altivec’, ‘spe’, ‘no-spe’, ‘ibmlongdouble’, ‘ieeelongdouble’, ‘elfv1’, ‘elfv2’. -mabi=spe-mabi=no-spe-mabi=ibmlongdouble-mabi=ieeelongdouble-mabi=elfv1-mabi=elfv2-mprototype-mno-prototypeCR) to indicate whether floating-point values are passed in the floating-point registers in case the function takes variable arguments. With -mprototype, only calls to prototyped variable argument functions set or clear the bit. -msimsim-crt0.o and that the standard C libraries are libsim.a and libc.a. This is the default for ‘powerpc-*-eabisim’ configurations. -mmvmecrt0.o and the standard C libraries are libmvme.a and libc.a. -madscrt0.o and the standard C libraries are libads.a and libc.a. -myellowknifecrt0.o and the standard C libraries are libyk.a and libc.a. -mvxworks-membPPC_EMB bit in the ELF flags header to indicate that ‘eabi’ extended relocations are used. -meabi-mno-eabi-meabi means that the stack is aligned to an 8-byte boundary, a function __eabi is called from main to set up the EABI environment, and the -msdata option can use both r2 and r13 to point to two separate small data areas. Selecting -mno-eabi means that the stack is aligned to a 16-byte boundary, no EABI initialization function is called from main, and the -msdata option only uses r13 to point to a single small data area. The -meabi option is on by default if you configured GCC using one of the ‘powerpc*-*-eabi*’ options. -msdata=eabiconst global and static data in the .sdata2 section, which is pointed to by register r2. Put small initialized non-const global and static data in the .sdata section, which is pointed to by register r13. Put small uninitialized global and static data in the .sbss section, which is adjacent to the .sdata section. The -msdata=eabi option is incompatible with the -mrelocatable option. The -msdata=eabi option also sets the -memb option. -msdata=sysv.sdata section, which is pointed to by register r13. Put small uninitialized global and static data in the .sbss section, which is adjacent to the .sdata section. The -msdata=sysv option is incompatible with the -mrelocatable option. -msdata=default-msdata-meabi is used, compile code the same as -msdata=eabi, otherwise compile code the same as -msdata=sysv. -msdata=data.sdata section. Put small uninitialized global data in the .sbss section. Do not use register r13 to address small data however. This is the default behavior unless other -msdata options are used. -msdata=none-mno-sdata.data section, and all uninitialized data in the .bss section. -mblock-move-inline-limit=num
memcpy or structure copies) less than or equal to num bytes. The minimum value for num is 32 bytes on 32-bit targets and 64 bytes on 64-bit targets. The default value is target-specific. -G num
-mregnames-mno-regnames-mlongcall-mno-longcallshortcall function attribute, or by #pragma
longcall(0). Some linkers are capable of detecting out-of-range calls and generating glue code on the fly. On these systems, long calls are unnecessary and generate slower code. As of this writing, the AIX linker can do this, as can the GNU linker for PowerPC/64. It is planned to add this feature to the GNU linker for 32-bit PowerPC systems as well.
On Darwin/PPC systems, #pragma longcall generates jbsr
callee, L42, plus a branch island (glue code). The two target addresses represent the callee and the branch island. The Darwin/PPC linker prefers the first address and generates a bl
callee if the PPC bl instruction reaches the callee directly; otherwise, the linker generates bl L42 to call the branch island. The branch island is appended to the body of the calling function; it computes the full 32-bit address of the callee and jumps to it.
On Mach-O (Darwin) systems, this option directs the compiler emit to the glue for every direct call, and the Darwin linker decides whether to use or discard it.
In the future, GCC may ignore all longcall specifications when the linker is known to generate glue.
-mtls-markers-mno-tls-markers__tls_get_addr with a relocation specifying the function argument. The relocation allows the linker to reliably associate function call with argument setup instructions for TLS optimization, which in turn allows GCC to better schedule the sequence. -pthread-mrecip-mno-recip-ffast-math option when using -mrecip (or at least -funsafe-math-optimizations, -finite-math-only, -freciprocal-math and -fno-trapping-math). Note that while the throughput of the sequence is generally higher than the throughput of the non-reciprocal instruction, the precision of the sequence can be decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994) for reciprocal square roots. -mrecip=opt
! to invert the option: all’default’-mrecip. none’-mno-recip. div’divf’divd’rsqrt’rsqrtf’rsqrtd’So, for example, -mrecip=all,!rsqrtd enables all of the reciprocal estimate instructions, except for the FRSQRTE, XSRSQRTEDP, and XVRSQRTEDP instructions which handle the double-precision reciprocal square root calculations.
-mrecip-precision-mno-recip-precision-mcpu=power6, -mcpu=power7 or -mcpu=power8 automatically selects -mrecip-precision. The double-precision square root estimate instructions are not generated by default on low-precision machines, since they do not provide an estimate that converges after three steps. -mveclibabi=type
mass’, which specifies to use IBM's Mathematical Acceleration Subsystem (MASS) libraries for vectorizing intrinsics using external libraries. GCC currently emits calls to acosd2, acosf4, acoshd2, acoshf4, asind2, asinf4, asinhd2, asinhf4, atan2d2, atan2f4, atand2, atanf4, atanhd2, atanhf4, cbrtd2, cbrtf4, cosd2, cosf4, coshd2, coshf4, erfcd2, erfcf4, erfd2, erff4, exp2d2, exp2f4, expd2, expf4, expm1d2, expm1f4, hypotd2, hypotf4, lgammad2, lgammaf4, log10d2, log10f4, log1pd2, log1pf4, log2d2, log2f4, logd2, logf4, powd2, powf4, sind2, sinf4, sinhd2, sinhf4, sqrtd2, sqrtf4, tand2, tanf4, tanhd2, and tanhf4 when generating code for power7. Both -ftree-vectorize and -funsafe-math-optimizations must also be enabled. The MASS libraries must be specified at link time. -mfriz-mno-frizfriz instruction when the -funsafe-math-optimizations option is used to optimize rounding of floating-point values to 64-bit integer and back to floating point. The friz instruction does not return the same value if the floating-point number is too large to fit in an integer. -mpointers-to-nested-functions-mno-pointers-to-nested-functionsr11) when calling through a pointer on AIX and 64-bit Linux systems where a function pointer points to a 3-word descriptor giving the function address, TOC value to be loaded in register r2, and static chain value to be loaded in register r11. The -mpointers-to-nested-functions is on by default. You cannot call through pointers to nested functions or pointers to functions compiled in other languages that use the static chain if you use -mno-pointers-to-nested-functions. -msave-toc-indirect-mno-save-toc-indirect-mno-save-toc-indirect option is the default. -mcompat-align-parm-mno-compat-align-parmOlder versions of GCC (prior to 4.9.0) incorrectly did not align a structure parameter on a 128-bit boundary when that structure contained a member requiring 128-bit alignment. This is corrected in more recent versions of GCC. This option may be used to generate code that is compatible with functions compiled with older versions of GCC.
The -mno-compat-align-parm option is the default.
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Licensed under the GNU Free Documentation License, Version 1.3.
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